cache controller
英 [kæʃ kənˈtrəʊlə(r)]
美 [kæʃ kənˈtroʊlər]
网络 缓存控制器; 高速缓存控制器; 控制器; 快取控制器; 超高速缓存控制器
双语例句
- These classes delete selected elements from your cache when certain controller actions fire.
在某些控制器击发时，这些类会从缓存内删除选定的元素。 - For each cached element, you need only specify the content you want to cache, any controller action that produces your dynamic content, and a timeout.
对于每个被缓存的元素，只需指定想要缓存的内容、可生成动态内容的任何控制器动作以及超时。 - Cache data was lost, but the controller has recovered.
高速缓存数据丢失，但控制器已恢复。 - Cache incoherency means that the cache is unaware that the DMA controller has placed new words in memory.
这意味着缓存区无法辨别DMA控制器是否将新数据写入内存。 - Design of DDR2 Controller with the Cache of Reducing Writing Delay of DRAM Based on FPGA
基于FPGA实现的带有减小DRAM写延迟的Cache的DDR2控制器的设计 - Using sector cache, we can reduce the area of cache controller while meet the performance request.
因此，采用SectorCache就可以在满足性能要求的前提下尽可能减小Cache控制器的面积。 - Research on the Multi-Level Cache in the RAID Controller
RAID控制器中多级Cache的研究 - Firstly, TS-1 memory system architecture is introduced. Then some of the critical issue during the process of design and implementation are covered, including the design of Cache system and memory controller.
介绍了TS-1存储系统的体系结构，针对设计和实现过程中的关键问题进行了讨论，包括Cache系统的设计和存储控制器的设计。 - Design of Cache Controller with Harvard Architecture
哈佛体系结构的Cache控制器设计 - In our self-determined design of YHFT_D1, the Second Level Cache Controller ( L2), which is programmable, has been adopted.
在我们自主研制的YHFTD1中采用片内两级Cache层次，且二级Cache控制器（简称L2）是可编程控制的。 - In this paper, the instruction FIFO in the SDRAM controller is introduced. Full utilized the pipeline characteristic of the SDRAM, the performance of the no cache embedded microprocessor is improved.
本文提出了SDRAM预取FIFO的设计，充分利用SDRAM的流水特性，提高无Cache嵌入式处理器性能。 - Completed the design of the "Longtium D2" L2 cache, including the architecture design, hardware support, interconnection mechanism and the state machine of main controller etc.
完成了龙腾D2双核处理器中二级Cache的设计，包括整体结构的设计、硬件支持、互联机制、主控状态机的设计等。 - The Design and Study of Level Two Cache Controller on High Performance DSP Chip
高性能DSP片内二级Cache控制器设计研究 - Base on Cache system, proposes the data reload strategy which using cyclic redundancy codes. Implements the high reliability Cache controller which using cyclic redundancy codes to check error in Cache memory and data reload to correct the error. 4.
三.根据Cache系统的情况，提出了基于循环码校验的数据重载策略，实现了用循环码来检测Cache中的错误并通过数据重载更新错误数据的高可靠Cache控制器。 - This thesis is based on a DSP design project in XX research institute, including two parts of work: cache controller design and cache memory design.
本文的研究工作以XX研究所的xxDSP项目为基础，分为两个部分：cache控制器设计和cache存储器的设计。 - In the design of the cache controller of Harvard architecture, the 4-way associated mapping algorithm is adopted.
在哈佛结构的cache控制器设计中，映射算法采用4路组相联的映射算法。